Dynamic random access memory "one-device" cells, consisting of a storage capacitor and a single transistor controlling the charge/discharge of the capacitor, were first disclosed in commonly-assigned U.S. Pat. No. 3,387,286, to Dennard. Since then, a host of related designs have proliferated in the memory art. In general, these designs have been directed to increasing the storage capacitance of the capacitor, or decreasing the amount of chip area that is taken up by each memory cell.
A combination of these trends in the art has led to the development of the so-called "trench storage cell." A trench or groove is defined in a silicon substrate, and is filled with a conductive material such as polysilicon. Since the size of the capacitor electrode has increased without taking up chip surface area, a greater amount of charge can be stored in a smaller area. Among the first disclosures of this general idea were an article by Clarke et al, entitled "Capacitor For Single FET Memory Cell," IBM Technical Disclosure Bulletin, Vol. 17, No. 9, February 1975, pp. 2579-2580 (in FIG. 2, polysilicon 22 is formed within an insulated groove to provide an enhanced storage capacitance), and an article by Dockerty, entitled "High-Capacitance, One-Device Cell," IBM Technical Disclosure Bulletin, Vol. 19, No. 2, July 1976, p. 506 (in FIG. 3, a 5 .mu.m trench is filled with "porus silicon" to enhance storage capacitance).
Other teachings in the art have "shared" the capacitance produced by a filled trench between two adjacent FETs. This has further reduced the amount of chip space utilized per memory cell. See the abovecited Clarke article, in which either side of the V-groove trench forms the storage capacitor for adjacent memory cells. Japanese Published Patent Application JP No. 61-068,647 (published Apr. 19, 1985, based on Japanese Patent Application JP No. 58-177,231, filed Sept. 26, 1983) apparently discloses a trench cell in which the poly-filled trench is etched such that two separate polysilicon structures are formed on each sidewall of the trench. The structures are separated by air. Each structure appears to form a plate electrode for a capacitor associated with an adjacent FET. The capacitor appears to provide an inversion region which provides charge to a drain region when a channel is induced in the FET. See U.S. Pat. No. 4,329,704 (issued May 11, 1982 to Sakurai et al) for a teaching of a "buried" storage capacitor.
In some cases, the use of the word "trench" may be a misnomer. Many of the so-called "trenches" are actually discrete apertures that are formed in the substrate. See e.g. an article by Nakajima et al, "An Isolation-Merged Vertical Capacitor Cell For Large Capacity DRAM," IEDM Digest of Technical Papers 1984, Paper 9.4, pp. 240-243. In FIG. 2 the "trench" that is filled with discrete layers of poly is shown as being a square aperture. More recently, trench cells have been proposed in which an elongated aperture (i.e., a true "trench") is filled with polysilicon to define a plurality of sidewall capacitors. See Furuyama et al, "A Vertical Capacitor Cell For Large Capacity DRAM," VLSI Symposium on Integrated Circuits, September 1984, Paper 1-7, pp. 16-17, in which an elongated trench is filled with polysilicon to form a series of memory cells. Adjacent cells are isolated by orthogonal trenches that are filled with silicon dioxide. See also U.S. Pat. No. 4,369,564 (issued Jan. 25, 1983 to Hiltpold), wherein a single V-groove is shared by two adjacent memory cells, the midpoint of the groove having a thicker layer of oxide in order to separate the adjacent cells from each other; U.S. Pat. No. Re. 32,090 (issued Mar. 4, 1986 to Jaccodine), wherein parallel polysilicon-filled trenches have FETs disposed between them, one side of each trench providing a storage capacitor for the FET and the other side of each trench being isolated from the next FET by a channel stop region; and European Patent Application EP No. 150,597 (published Aug. 7, 1985, based on Japanese Patent Application No. 59-004,364), wherein parallel trenches are alternatively filled with capacitor defining polysilicon layers and an isolating layer, such that every other trench isolates adjacent polyfilled trenches from one another.
The general idea of the so-called "sidewall structures" is also known in the art. As disclosed in commonly-assigned U.S. Pat. No. 4,256,514 (issued Mar. 17, 1981 to Pogge et al), a conformal film of material is coated on a "block" or "mandrel structure" that has an upper horizontal surface and vertical surfaces. The film is directionally etched such that it is removed from the horizontal surface of the mandrel. The remaining conformal material forms a sidewall-defined structure that has a horizontal width which is controlled as a function of the original film thickness of the material. In U.S. Pat. No. 4,322,883 (issued Apr. 6, 1982 to Abbas et al and assigned to the assignee of the present invention), this general idea is used to define polysilicon sidewall-defined structures 28, which are then oxidized to form sidewalls 30 for isolating adjacent bipolar contacts from one another. A residual portion of the original sidewall may be left in place (it is not critical to the operation of the device). See also U.S. Pat. No. 4,378,627 (issued Apr. 5, 1983 to Jambotkar and assigned to the assignee of the present invention), wherein sidewall regions 26 are defined in N+ silicon regions 18 to provide isolation from an overlaying N+ layer 30 that is subsequently etched to define a gate electrode; and U.S. Pat. No. 4,419,809 (issued Dec. 13, 1983 to Riseman et al and assigned to the assignee of the present invention), wherein conductive sidewall structures 26 form the gate electrodes of FETs. Note that in FIG. 11 of the Riseman patent, the mandrel structure that is used to define the sidewall structures is formed over a semi-recessed oxidation region 12, such that the gate electoodes are spaced from either side of region 12. Finally, note that in the above-cited pending U.S. patent application Ser. No. 885,618, sidewall structures are formed within a partially-filled trench to define the gate electrodes of the FETs associated with the storage capacitors defined by the lower portions of each side of the trench.
Heretofore, the present inventor is unaware of any known teachings that relate to utilizing sidewall structures to efficiently define bridge contacts and gate electrodes on either side of a completely filled trench, in which the conductive materials coated within the trench extend above the surface of the substrate to define a mandrel structure.